1. Field of the Invention
The present invention relates to a semiconductor memory that requires a regular refresh operation.
2. Description of the Related Art
A semiconductor memory such as a DRAM (Dynamic Random Access Memory) has a redundancy memory cell row (redundancy circuit) for relieving defects of memory cell rows occurring in a process of manufacturing semiconductor memories in order to increase a yield and reduce chip costs. Defects of memory cell rows are relieved by replacing defective memory cell rows with redundancy cell rows in a test process.
One example of methods of replacing defective memory cell rows with redundancy memory cell rows may include a replace redundancy method. A semiconductor memory employing the replace redundancy method has a ROM (Read Only Memory) such as a fuse circuit that stores addresses of defective memory cell rows. In the replace redundancy method, the ROM has a high degree of freedom for its arrangement since word lines (word drivers) are connected to a word decoder without the ROM. For this reason, for example, if the semiconductor memory has a plurality of memory cell arrays, it is easy to form the word decoder in common. Accordingly, the replace redundancy method is effective for the reduction of a chip size.
On the other hand, in a DRAM or the like, a memory cell requires a refresh operation for rewriting data of the memory cell at a regular period since the memory cell stores the data by means of charges accumulated in a capacitor. A semiconductor memory employing a shift refresh method in order to reduce power consumption during a refresh operation is disclosed in Japanese Unexamined Patent Application Publication No. 2000-311487, for example. This kind of semiconductor memory sequentially selects word lines to be refreshed by using a shift register during the refresh operation. Accordingly, there is no need of a refresh address generating circuit, such as a refresh counter, and a switching circuit for switching between an external address and a refresh address. As a result, it is possible to reduce an increase in the chip size and power consumption during a refresh operation.
The inventor has studied the introduction of the shift refresh method into a semiconductor memory that employs the replace redundancy method. If the shift refresh method is simply applied to the semiconductor memory that employs the replace redundancy method, defective memory cell rows are refreshed while redundancy memory cell rows are in use, or the redundancy memory cell rows are refreshed while the redundancy memory cell rows are not in use. Since word lines that require no activation are activated during a refresh operation, a charge and discharge current is unnecessarily consumed. That is, the effect of reducing power consumption by the shift refresh method during the refresh operation is lowered. In addition, the activation of word lines of the defective memory cell rows during the use of the redundancy memory cell rows may cause stored data in other memory cell rows to be destroyed if the defects of the memory cell rows are due to a word decoder or a short between word lines, between word lines and bit lines, or between memory cells.